Scott Irving
Contact
-
Phone+1-207-358-8272 (Work)+1-207-838-9624 (Cell)+1-207-838-9624 (Home)
Biography
Substantial experience in semiconductor engineering, including executive level management. My work includes plasma etch, thin films, ion implant, photolithography, and process development, TCAD, and CAD. Experience includes silicon and III-V devices. See my LinkedIn profile for details (http://www.linkedin.com/in/scottirving)
Technical Expertise
Special Skills
Technical Specialties
Simulation of semiconductor devices using Synopsys's Sentaurus and Taurus tool sets, as well as Silvaco or other vendors. Experience with bipolar, cmos devices includes digital, analog, and power. Optical device experience for solar, photodetectors, and LED including core device, thermal, and ray tracing. Simulation of passive and parasitic devices. Design of test chips for calibration of simulators and characterization of process technologies and devices. Automation of test chip design.
Additional Specialties
Synopsys Sentaurus and Taurus tools have been my primary focus. I also have experience with Silvaco.
Interests
Experience
Owner/Partner
Petrus Technology LLC
Publications
Yuanxiang Zhang, Lihua Liang Xuefan Chen Yong Liu Luk, T., and Irving, S., "Impact of the UBM geometry and solder bump shape on electromigration reliability in a package system," in Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems, 2009. EuroSimE 2009. 10th International Conference on, 2009, pp. 1 - 6.
Yong Liu, Luk, T., and Irving, S., "Parameter Modeling for Wafer Probe Test," Electronics Packaging Manufacturing, IEEE Transactions on, vol. 32, no. 2, pp. 81 - 88, 2009.
Yong Liu, Qian, R. Quinones, C. Irving, S., and Luk, T., "Impact of manufacturing variation on the reliability/quality of an Opto-BGA system in package," in Electronic Components and Technology Conference, 2009. ECTC 2009. 59th, 2009, pp. 196 - 200.
Yong Liu, Qiang Wang Lihua Liang Xuefan Chen Irving, S., and Luk, T., "A new prediction methodology for electromigration-induced solder degradation in a WL-CSP system," in Electronic Components and Technology Conference, 2009. ECTC 2009. 59th, 2009, pp. 269 - 276.
Yumin Liu, Carredo, M. Zhiping Hu Yong Liu Luk, T., and Irving, S., "Effect of wire bond and die layout on electrical performance of power packages," in Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems, 2009. EuroSimE 2009. 10th International Conference on, 2009, pp. 1 - 6.
Education
Rensselaer Poly Institute
Master of Science
Physical Sciences
, 1984