Mr. Prantik Mahajan Senior Member

Dresden, Sachsen , Germany  •  IEEE Germany Section
Biography
An ESDA Device Stress Test Certified professional with 14+ years of rich experience in the semiconductor industry from Chip Design to Manufacturing, ESD & Reliability and 4 years of Graduate Research experience. Currently working on Renesas product-level ESD protection strategy, architecture & network definition, design & development, interfacing with Foundries and Customers worldwide. Worked across a spectrum of Technology Nodes - right from 180nm down to 10nm (Bulk CMOS, SOI, BCD, GaN & FINFET) spanning across a broad customer base. Hard-working individual with pronounced focus on details. Meticulous data analyst with interest beyond Technology & Design into the areas of Device Physics, ESD & Reliability. A prolific Inventor with multiple Patents (published/pending/filed) and several Publications and Invited Talks (published/presented/accepted) encompassing major conferences and journals.
Certifications
ESDA Device Stress Testing Certification
Interests
Electrostatic discharges
Experience
Chief Engineer/Chief Scientist
Renesas Electronics Corp
IEEE Volunteer Positions
Past Positions
Chair
Heritage Institute of Technology-Kolkata
Dec 2005 - Dec 2009
Publications
Prantik Mahajan, Tarkeshwar C Patil, and Subhananda Chakrabarti, "HWCVD-grown Silicon Nanocrystals : A study of the effect of annealing on structures evolved with varying growth rates," MRS Proceedings.
Prantik Mahajan, Satya SureshAlfred QuahFransiscus RivaiRuchil JainUpinder Singh, et al., "Robust ESD Implanted 5V GGNMOS Clamp Design and Process optimization with maximized ESD Design Window," in 2019 Electron Devices Technology and Manufacturing Conference (EDTM), pp. 172 - 175.
Prantik Mahajan, Raunak KumarRobert Gauthier, and Kyong Jin Hwang, "Optimization of GGNMOS Devices for High-Voltage ESD Protection in BCDLite Technology," in 2020 International EOS/ESD Symposium on Design and System (IEDS), pp. 1 - 6.
Prantik Mahajan, Aloysius Priartanto HerlambangKyong Jin Hwang, and Robert Gauthier, "A Novel Buried Floating PESD-doped NPN-eSCR Device for Robust High-Voltage ESD Protection," in 2021 43rd Annual EOS/ESD Symposium (EOS/ESD), pp. 1 - 7.
Tarkeshwar C. Patil, Prantik Mahajan, and S. Chakrabarti, "Effect of progressive annealing on Silicon Nanostructures grown by Hot Wire Chemical Vapor Deposition," Superlattices and Microstructures.
Education
Indian Institute of Technology - Bombay
Master of Engineering
Engineering , 2010
Heritage Institute Of Technology - Kolkata
Bachelor of Technology
Engineering , 2006