CONTACT THE ESD CONSULTANT ENGINEER AT ::: p-koeppen@esdunlimited.com ::: More than 10 years of experience with ESD problem solutions for customer CMOS or other technology System On Chip (SOC) and Intellectual Property (IP) integrated circuit design for component Electro Static Discharge (ESD), Human Body Model (HBM), Charge Device Model (CDM), Latch Up (LU), Electrical Overstress (EOS), and System ESD protection robustness. Submit and debug compliance testing results according to ANSI/ESDA/JEDEC JS-002-2014 or ANSI/ESDA/JEDEC JS-001-2014 for HBM and CDM. Review printed circuit board topologies of all board components for System Electro Static Discharge (ESD) protection robustness for compliance testing according to IEC 61000-4-2, ISO 10605 or IEC 61000-4-4. Review and debug all integrated circuit (IC) Chip level topological areas for Latch-Up ( LU ) robustness. Submit and debug compliance testing for Latch Up according to JESD78D or AEC_Q100-004D. Debug any Component ESD, System ESD or LU stress testing failures and provide corrective actions to these failures. Debug any EOS (Electrical Overstress) failures and provide corrective actions to these failures.

Experience using Spice circuit simulator, EDA tools for Latch Up robustness checking and EDA tools for component ESD (HBM, CDM) implementation checking.