Expertise from algorithm development to DSP software and FPGA firmware implementation in custom embedded hardware. Recent work focused on ultra high bandwidth high dynamic range applications from UHF to EHF. Systems experience in algorithm development, simulation, and analysis of Jamming and Cancellers, Direction Finding and Beamforming, Transmitters and Receivers, and Hardware in the Loop Testing. Designed mixed signal CompactPCI Serial System/Peripheral cards. Latest design features a Xilinx Zynq UltraScale+ FPGA with DDR-4, PCIe, Gigabit Ethernest, USB, SDHC, and 16.3 Gbps SERDES connect to our full mesh backplane. High isolation analog interfaces include a dual 1.25 GSPS 14-bit ADC and two 2.5 GSPS 16-bit DACs. Runs U-boot, GNU/Linux, BLAS, and LAPACK with a SCPI control protocol. Programmable personalities include: Filter-Equalizer, Frequency Tracking Band Pass/Reject Filter, Fading/Target Emulator, MIMO/Phased Array Channel Emulator, or Time Delay Beamformer. Equipment includes: 500 MHz logic analyzer, 600 MHz oscilloscope, 3 GHz vector network analyzer, 3 GHz spectrum analyzer, many JTAG cables, plus soldering irons and hot air for PCB rework. Software includes LabVIEW, Matlab, Maxima, Xilinx Vivado/Altera Quartus II/Lattice Diamond, and DxDesigner/Pads/HyperLynx 3D EM.

Software Tool Expertise in GNU/Linux, MS Windows, Embedded Linux, Linux kernel, U-Boot, LAPACK (Linear Algebra Package), BLAS (Basic Linear Algebra Subprograms), C/C++, embedded C/C++, Matlab, Maxima, Scilab, FPGA Verilog, Xilinx Vivado, Altera Quartus II, Lattice Diamond, ModelSim, DxDesigner, IODesigner, HyperLynx 3D EM, LabVIEW. Verilog Modules include: Arbitrary Waveform Generators, Notch Filters and Cancellers, and DSP functions. Phased array simulation supports: transformations between WGS 84, ECEF, and Local coordinates; source and receiver location and orientation, antenna models; RF signal processing (filtering, down conversion, nonlinearity, noise); GPS satellite models and receiver simulations; and portable linear algebra libraries for simulation and embedding of DSP algorithms.